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1 file number 3961.3 hs-rtx2010rh radiation hardened real time express microcontroller the hs-rtx2010rh is a radiation-hardened 16-bit microcontroller with on-chip timers, an interrupt controller, a multiply-accumulator, and a barrel shifter. it is particularly well suited for space craft environments where very high speed control tasks which require arithmetically intensive calculations, including ?ating point math to be performed in hostile space radiation environments. this processor incorporates two 256-word stacks with multitasking capabilities, including con?urable stack partitioning and over/under?w control. instruction execution times of one or two machine cycles are achieved by utilizing a stack oriented, multiple bus architecture. the high performance asic bus, which is unique to the rtx product, provides for extension of the microcontroller architecture using off-chip hardware and application speci? i/o devices. rtx microcontrollers support the c and forth programming languages. the advantages of this product are further enhanced through third party hardware and software support. combined, these features make the hs-rtx2010rh an extremely powerful processor serving numerous applications in high performance space systems. the hs-rtx2010rh has been designed for harsh space radiation environments and features outstanding single event upset (seu) resistance and excellent total dose response. speci?ations for rad hard qml devices are controlled by the defense supply center in columbus (dscc). the smd numbers listed here must be used when ordering. detailed electrical speci?ations for these devices are contained in smd 5962-95635. a ?ot-link?is provided on our homepage for downloading. www.intersil.com/spacedefense/space.asp features electrically screened to smd # 5962-95635 qml quali?d per mil-prf-38535 requirements fast 125ns machine cycle 1.2 m tsos4 cmos/sos process total dose capability . . . . . . . . . . . . . . . . . . 300krad(si) single event upset critical let . . . . . . . >120mev/mg/cm 2 single event upset error rate . . . . <1 x 10 -10 errors/bit-day (note) -55 o c - 125 o c, 5v 10% operation single cycle instruction execution fast arithmetic operations - single cycle 16-bit multiply - single cycle 16-bit multiply accumulate - single cycle 32-bit barrel shift - hardware floating point support c software development environment direct execution of fourth language single cycle subroutine call/return four cycle interrupt latency on-chip interrupt controller three on-chip 16-bit timer/counters two on-chip 256 word stacks asic bus for off-chip architecture extension 1 megabyte total address space word and byte memory access fully static design - dc to 8mhz operation 84 lead quad flat package or 85 pin grid array third party software and hardware development systems note: single event upset error rates are adams 10% worst case environment under worst case conditions for upset. applications space systems embedded control digital filtering image processing scienti? instrumentation optical systems control systems attitude/orbital control ordering information ordering number internal mkt. number temp. range ( o c) 5962f9563501qxc HS8-RTX2010RH-8 55 to 125 5962f9563501qyc hs9-rtx2010rh-8 55 to 125 5962f9563501v9a hs0-rtx2010rh-q 25 5962f9563501vxc hs8-rtx2010rh-q 55 to 125 5962f9563501vyc hs9-rtx2010rh-q 55 to 125 hs8-rtx2010rh/proto hs8-rtx2010rh/proto 55 to 125 hs9-rtx2010rh/proto hs9-rtx2010rh/proto 55 to 125 data sheet march 2000 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | copyright intersil corporation 2000 real time express, rtx, and asic bus are trademarks of intersil corporation.
2 block diagram hs-rtx2010rh inputs control clock and configuration control main memory off chip peripherals interrupt inputs interrupt control timer inputs asic bus interface memory bus interface processor rtx core stack controllers barrel shifter mac return stack 256-word parameter stack 256-word memory page control timer/ counters pinouts hs8-rtx2010rh mil-std-1835 cmga3-p85c note: an overbar on a signal name represents an active low signal. b acdefghjkl ga00 md14 md12 md11 md08 inta tclk e i5 gd15 md05 gnd gnd md04 md03 md02 gd07 md00 new md01 vdd lds uds gnd ma18 gnd ma04 ma08 gd05 ma10 ma13 ma15 ma17 ma19 ma05 ma07 gd04 ma09 ma12 vdd ma14 ma16 ma06 ma11 gnd gd09 boot pclk gd01 ma01 ga01 vdd md06 ga02 iclk md15 md13 md10 md09 md07 nmi gnd abcdefghjkl vdd ma02 ma03 e i1 e i2 gd14 gd11 gd10 e i4 e i3 wait gd13 gd12 gd06 gd03 gd02 gd00 gd08 int- sup 1 10 11 4 3 7 8 9 5 6 2 reset pin a1 gr/ w gio mr/ w hs-rtx2010rh top view pins down 8 9 10 11 2 3 4 5 1 7 6 c j k lhgfedba c j k lhgfedba pin a1 bottom view pins up ga00 md14 md12 md11 md08 tclk gd15 md05 gnd gd13 gd14 gnd md04 md03 md02 gd12 gd11 gd07 md00 new md01 gd06 vdd lds gnd ma18 gnd gd03 ma04 ma08 gd05 ma10 ma13 ma17 ma19 gd02 gd01 ma02 ma05 ma07 gd04 ma16 gd08 gd10 gd09 boot ga01 vdd md06 ga02 md15 md13 md10 md09 md07 e i4 e i1 gnd iclk uds pclk ma15 intsup nmi wait reset e i3 e i2 vdd inta e i5 ma09 ma12 ma14 gd00 ma01 ma03 ma06 ma11 gnd vdd mr/ w gr/ w gio align. pin hs-rtx2010rh
3 hs9-rtx2010rh (lead length not to scale) see intersil outline r84.a pinouts (continued) note: an overbar on a signal name represents an active low signal. hs-rtx2010rh top view 65 66 67 68 69 70 71 72 73 74 54 55 56 57 58 59 60 61 62 64 63 md02 md03 md04 gnd md05 md06 md07 vdd md08 ma17 ma18 ma19 gnd lds uds new boot pclk md00 md01 75 76 77 78 79 80 81 82 83 84 1 2 3 4 5 6 7 8 9 10 11 25 26 27 28 29 30 31 32 12 13 14 18 19 20 21 22 23 24 15 16 17 53 52 51 50 33 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 ei5 md09 md10 md11 md12 md13 md14 gnd md15 ga00 ga01 ga02 tclk inta nmi intsup vdd ei1 ei2 ei3 ei4 ma04 ma03 ma02 ma01 gd00 gd01 gd02 ma16 ma15 ma14 ma13 vdd ma12 ma11 ma10 ma09 gnd ma08 ma07 ma06 ma05 reset wait iclk gd14 gd13 gnd gd12 gd11 gd10 gd09 gd08 gd07 vdd gd06 gd05 gd04 gd03 gnd gd15 gr/ w gio mr/ w pga and cqfp pin/signal assignments cqfp pga pin signal name type 1 c6 ga02 output; address bus 2 a6 tclk output 3 a5 inta output 4 b5 nmi input 5 c5 intsup input 6 a4 vdd power 7 b4 ei1 input 8 a3 ei2 input 9 a2 ei3 input 10 b3 ei4 input 11 a1 ei5 input 12 b2 reset input 13 c2 wait input 14 b1 iclk input 15 c1 gr/w output 16 d2 gio output 17 d1 gd15 i/o; data bus 18 e3 gd14 i/o; data bus 19 e2 gd13 i/o; data bus 20 e1 gnd ground 21 f2 gd12 i/o; data bus 22 f3 gd11 i/o; data bus 23 g3 gd10 i/o; data bus 24 g1 gd09 i/o; data bus 25 g2 gd08 i/o; data bus 26 f1 gd07 i/o; data bus 27 h1 vdd power 28 h2 gd06 i/o; data bus 29 j1 gd05 i/o; data bus 30 k1 gd04 i/o; data bus 31 j2 gd03 i/o; data bus 32 l1 gnd ground 33 k2 gd02 i/o; data bus 34 k3 gd01 i/o; data bus 35 l2 gd00 i/o; data bus 36 l3 ma01 output; address bus 37 k4 ma02 output; address bus 38 l4 ma03 output; address bus 39 j5 ma04 output; address bus 40 k5 ma05 output; address bus 41 l5 ma06 output; address bus 42 k6 ma07 output; address bus 43 j6 ma08 output; address bus 44 j7 gnd ground 45 l7 ma09 output; address bus 46 k7 ma10 output; address bus pga and cqfp pin/signal assignments (continued) cqfp pga pin signal name type hs-rtx2010rh
4 47 l6 ma11 output; address bus 48 l8 ma12 output; address bus 49 k8 ma13 output; address bus 50 l9 vdd power 51 l10 ma14 output; address bus 52 k9 ma15 output; address bus 53 l11 ma16 output; address bus 54 k10 ma17 output; address bus 55 j10 ma18 output; address bus 56 k11 ma19 output; address bus 57 j11 gnd ground 58 h10 lds output 59 h11 uds output 60 f10 new output 61 g10 boot output 62 g11 pclk output 63 g9 mr/w output 64 f9 md00 i/o; data bus 65 f11 md01 i/o; data bus pga and cqfp pin/signal assignments (continued) cqfp pga pin signal name type 66 e11 md02 i/o; data bus 67 e10 md03 i/o; data bus 68 e9 md04 i/o; data bus 69 d11 gnd ground 70 d10 md05 i/o; data bus 71 c11 md06 i/o; data bus 72 b11 md07 i/o; data bus 73 c10 vdd power 74 a11 md08 i/o; data bus 75 b10 md09 i/o; data bus 76 b9 md10 i/o; data bus 77 a10 md11 i/o; data bus 78 a9 md12 i/o; data bus 79 b8 md13 i/o; data bus 80 a8 md14 i/o; data bus 81 b6 gnd ground 82 b7 md15 i/o; data bus 83 a7 ga00 output; address bus 84 c7 ga01 output; address bus - c3 - isolated alignment pin pga and cqfp pin/signal assignments (continued) cqfp pga pin signal name type output signal descriptions signal cqfp reset level description outputs new 60 1 new: a high on this pin indicates that an instruction fetch is in progress. boot 61 1 boot: a high on this pin indicates that boot memory is being accessed. this pin can be set or reset by accessing bit 3 of the configuration register. mr/w 63 1 memory read/write: a low on this pin indicates that a memory write operation is in progress. uds 59 1 upper data select: a high on this pin indicates that the high byte of memory (md15-md08) is being accessed. lds 58 1 lower data select: a high on this pin indicates that the low byte of memory (md07-md00) is being accessed. gio 16 1 asic i/o: a low on this pin indicates that an asic bus operation is in progress. gr/w 15 1 asic read/write: a low on this pin indicates that an asic bus write operation is in progress. pclk 62 0 processor clock: runs at half the frequency of iclk. all processor cycles begin on the rising edge of pclk. held low extra cycles when wait is asserted. tclk 2 0 timing clock: same frequency and phase as pclk but continues running during wait cycles. inta 3 0 interrupt acknowledge: a high on this pin indicates that an interrupt acknowledge cycle is in progress. input signal, bus, and power connection descriptions signal cqfp lead description inputs wait 13 wait: a high on this pin causes pclk to be held low and the current cycle to be extended. iclk 14 input clock: internally divided by 2 to generate all on-chip timing (cmos input levels). reset 12 a high level on this pin resets the rtx. must be held high for at least 4 rising edges of iclk plus 12 iclk cycle setup and hold times. hs-rtx2010rh
5 ei2, ei1 8, 7 external interrupts 2, 1: active high level-sensitive inputs to the interrupt controller. sampled on the rising edge of pclk. see timing diagrams for detail. ei5-ei3 11-9 external interrupts 5, 4, 3: dual purpose inputs; active high level-sensitive interrupt controller inputs; active high edge-sensitive timer/counter inputs. as interrupt inputs, they are sampled on the rising edge of pclk. see timing diagrams for detail. nmi 4 non-maskable interrupt: active high edge-sensitive interrupt controller input capable of interrupting any processor cycle when nmi is set to mode 0. see the interrupt suppression and interrupt controller sections. intsup 5 interrupt suppress: a high on this pin inhibits all maskable interrupts, internal and external. address buses (outputs) ga02 1 asic address: 3-bit asic address bus, which carries address information for external asic devices. ga01 84 ga00 83 ma19-ma14 56-51 memory address: 19-bit memory address bus, which carries address information for main memory. ma13-ma09 49-45 ma08-ma01 43-36 data buses (i/o) gd15-gd13 17-19 asic data: 16-bit bidirectional external asic data bus, which carries data to and from off-chip i/o devices. gd12-gd07 21-26 gd06-gd03 28-31 gd02-gd00 33-35 md15 82 memory data: 16-bit bidirectional memory data bus, which carries data to and from main memory. md14-md08 80-74 md07-md05 72-70 md04-md00 68-64 power connections vdd 6, 27, 50, 73 power supply +5v connections. a 0.1 f, low impedance decoupling capacitor should be placed between vdd and gnd. this should be located as close to the rtx package as possible. gnd 20, 32, 44, 57, 69, 81 power supply ground return connections. input signal, bus, and power connection descriptions (continued) signal cqfp lead description figure 1. ac drive and measure points - clk input 4.0v 0.5v 4.0v 0.5v t pulse width t hold t setup 2.25v t valid t hold t delay 2.25v typical clock or strobe typical input typical output typical data output 2.25v 2.25v 2.75v 1.75v 2.75v 1.75v 2.25v 2.25v 2.25v t delay t pulse width hs-rtx2010rh
6 timing diagrams notes: 1. normal cycle: this waveform describes a normal pclk cycle and a pclk cycle with a wait state. 2. extended cycle: this waveform describes a pclk cycle for a user memory access or an external asic bus read cycle when the cycext bit or arce bit is set. 3. extended cycle: this waveform describes a gio cycle for an external asic bus read when the arce bit is set. 4. an active high signal on the reset input is guaranteed to reset the processor if its duration is greater than or equal to 4 rising edges of iclk plus 1/2 iclk cycle setup and hold times. if the reset input is active for less than four rising edges of iclk, the processor w ill not reset. figure 2. clock and wait timing figure 3. timer/counter timing t 3 iclk tclk wait pclk (note 2) pclk (note 1) gio (note 3) t 2 t 1 t 19 t 13 t 12 t 5 t 4 t 11 t 5 t 20 t 15 t 20 t 17 t 16 t 51 t 50 t 4 t 7 t 8 t 6 ei5 - ei3 hs-rtx2010rh
7 notes: 5. if both lds and uds are low, no memory access is taking place in the current cycle. this only occurs during streamed instructions that do not access memory. 6. during a streamed single cycle instruction, the memory data bus is driven by the processor. figure 4. memory bus timing notes: 7. gio remains high for internal asic bus cycles. 8. gr/ w goes low and gd is driven for all asic write cycles, including internal ones. 9. during non-asic write cycles, gd is not driven by the hs-rtx2010rh. therefore, it is recommended that all gd pins be pulled to vcc or gnd to minimize power supply current and noise. 10. t 40b and t 41b specifications are for streamed mode of operation only. figure 5. asic bus timing timing diagrams (continued) t 26 t 28 t 31 t 35 t 29 t 32 t 34 t 33 pclk ma md in md out lds uds new boot mr/ w t 21 t 22 t 48 t 50 t 51 t 49 t 52 t 56 t 54 t 58 t 42 t 43 t 40a, b t 41a, b t 62 t 61 t 63 t 65 ga pclk iclk gio gr/ w gd in gd out t 69 hs-rtx2010rh
8 notes: 11. events in an interrupt sequence are as follows: e 1 . the interrupt controller samples the interrupt request inputs on the rising edge of pclk. if nmi rises between e 1 and the rising edge of pclk prior to e 5 , the interrupt vector will be for nmi. e 2 . if any interrupt requests were sampled, the interrupt controller issues an interrupt request to the core on the falling edge o f pclk. e 3 . the core samples the state of the interrupt requests from the interrupt controller on the falling edge of pclk. if intsup is high, maskable interrupts will not be detected at this time. e 4 . when the core samples an interrupt request on the falling edge of pclk, an interrupt acknowledge cycle will begin on the next rising edge of pclk. e 5 . following the detection of an interrupt request by the core, an interrupt acknowledge cycle begins. the interrupt vector will be based on the highest priority interrupt request active at this time. 12. t 44 is only required to determine when the interrupt acknowledge cycle will occur. 13. interrupt requests should be held active until the interrupt acknowledge cycle for that interrupt occurs. figure 6. interrupt timing: with interrupt suppression figure 7. interrupt timing: with no interrupt suppression timing diagrams (continued) ma inta intsup pclk e 1 e 2 e 3 e 4 e 5 t 44 t 46 t 47 t 46 t 47 t 67 t 68 t 28 t 26 ei int vector e 1 e 2 e 4 e 5 t 44 t 46 t 47 t 67 t 68 t 26 t 28 ma inta intsup pclk ei int vector hs-rtx2010rh
9 hs-rtx2010rh microcontroller the hs-rtx2010rh is designed around the rtx processor core, which is part of the intersil standard cell library. this processor core has eight 16-bit internal registers, an alu, internal data buses, and control hardware to perform instruction decoding and sequencing. on-chip peripherals which the hs-rtx2010rh includes are memory page controller, an interrupt controller, three timer/counters, and two stack controllers. also included are a multiplier-accumulator (mac), a barrel shifter, and a leading zero detector for ?ating point support. off-chip user interfaces provide address and data access to main memory and asic i/o devices, user de?ed interrupt signals, and clock/reset controls. figure 9 shows the data paths between the core, on-chip peripherals, and off-chip interfaces. the hs-rtx2010rh microcontroller is based on a two-stack architecture. these two stacks, which are last-in-first-out (lifo) memories, are called the parameter stack and the return stack. two internal registers, and , provide the top two elements of the 16-bit wide parameter stack, while the remaining elements are contained in on-chip memory (?tack memory?. the top element of the return stack is 21 bits wide, and is stored in registers and , while the remaining elements are contained in stack memory. the highly parallel architecture of the rtx is optimized for minimal subroutine call/return overhead. as a result, a subroutine call takes one cycle, while a subroutine return is usually incorporated into the preceding instruction and does not add any processor cycles. this parallelism provides for peak execution rates during simultaneous bus operations which can reach the equivalent of 32 million forth language operations per second at a clock rate of 8mhz. typical execution rates exceed 8 million operations per second. intersil factory applications support for this device is limited. rts-c c-compiler support is provided by highland software at highlandsoft@compuserve.com. development system tools are supported by micro processor engineering limited (uk) at 441 703 631441. a hs-rtx2010rh programmers reference manual can be obtained through your local intersil sales of?e. notes: 14. events in an interrupt sequence are as follows: e 1 . the interrupt controller samples the interrupt request inputs on the rising edge of pclk. if nmi rises between e 1 and the rising edge of pclk prior to e 5 , the interrupt vector will be for nmi. e 2 . if any interrupt requests were sampled, the interrupt controller issues an interrupt request to the core on the falling edge o f pclk. e 4 . when the core samples an interrupt request on the falling edge of pclk, an interrupt acknowledge cycle will begin on the next rising edge of pclk. e 5 . following the detection of an interrupt request by the core, an interrupt acknowledge cycle begins. the interrupt vector will be based on the highest priority interrupt request active at this time. 15. t 44 is only required to determine when the interrupt acknowledge cycle will occur. 16. interrupt requests should be held active until the interrupt acknowledge cycle for that interrupt occurs. 17. nmi has a glitch filter which requires the signal that initiates nmi last at least two rising and two falling edges of iclk. figure 8. non-maskable interrupt timing timing diagrams (continued) t 44 e 1 e 2 e 4 e 5 pclk nmi ma inta nmi vector t 67 t 68 t 26 t 28 top next i ipr hs-rtx2010rh
10 hs-rtx2010rh operation control of all data paths and the program counter register, ( ), is provided by the instruction decoder. this hardware determines what function is to be performed by looking at the contents of the instruction register, ( ), and subsequently determines the sequence of operations through data path control. instructions which do not perform memory accesses execute in a single clock cycle while the next instruction is being fetched. as shown in figure 10, the instruction is latched into at the beginning of a clock cycle. the instruction is then decoded by the processor. all necessary internal operations are performed simultaneously with fetching the next instruction. instructions which access memory require two clock cycles to be executed. during the ?st cycle of a memory access instruction, the instruction is decoded, the address of the memory location to be accessed is placed on the memory address bus (ma19-ma01), and the memory data (md15-md00), is read or written. during the second cycle, alu operations are performed, the address of the next instruction to be executed is placed on the memory address bus, and the next instruction is fetched, as indicated in the bottom half of figure 10. byte swap hs-rtx2010rh off-chip user interfaces timer/counters tp0 tp1 tp2 tc0 tc1 tc2 alu yt pc i top cr md sr control stack imr ivr ibc control interrupt (note) control page memory clock and control reset interface memory bus interface asic bus dpr ipr upr cpr ubr spr sur svr ei5-ei3 ei2-ei1 inta nmi intsup iclk wait pclk tclk reset uds lds new boot mr/w ma19- ma01 md15- md00 gr/w gio ga2- ga0 gd15- gd00 - 1 +1 instruction decoder ir leading zero detector barrel shifter 16 x 16 mac mxr mhr mlr 256 x 21 return memory stack 256 x 16 parameter memory stack next note: contains the 5 most signi?ant bits (20-16) of the top element of the return stack. figure 9. hs-rtx2010rh functional block diagram ipr pc ir ir hs-rtx2010rh
11 rtx data buses and address buses the rtx core bus architecture provides for unidirectional data paths and simultaneous operation of some data buses. this parallelism allows for maximum ef?iency of data ?w internal to the core. addresses for accessing external (off-chip) memory or asic devices are output via either the memory data bus (ma19-ma01) or the asic address bus (ga02-ga00). see table 3. external data is transferred by the asic data bus (gd15-gd00) and the memory data bus (md15-md00), both of which are bidirectional. rtx internal registers the core of the hs-rtx2010rh is a macrocell available through the intersil standard cell library. this core contains eight 16-bit internal registers, which may be accessed implicitly or explicitly, depending upon the register accessed and the function being performed. : the top register contains the top element of the parameter stack++. is the implicit data source or destination for certain instructions, and has no asic address assignment. the contents of this register may be directed to any i/o device or to any processor register except the instruction register. is also the t input to the alu. input to must come through the alu. this register also holds the most signi?ant 16 bits of 32-bit products and 32-bit dividends. : the next register holds the second element of the parameter stack. is the implicit data source or destination for certain instructions, and has no asic address assignment. during a stack ?ush? the contents of are transferred to stack memory, and the contents of are put into . this register is used to hold the least signi?ant 16 bits of 32-bit products. memory data is accessed through , as described in the memory access section of this document. : the instruction register is actually a latch which contains the instruction currently being executed, and has no asic address assignment. in certain instructions, an operand can be embedded in the instruction code, making the implicit source for that operand (as in the case of short literals). input to this register comes from main memory (see tables 6 thru 22 for code information). : the con?uration register is used to indicate and control the current status/setup of the rtx microcontroller, through the bit assignments shown in figure 11. this register is accessed explicitly through read and write operations, which cause interrupts to be suppressed for one cycle, guaranteeing that the next instruction will be performed before an interrupt acknowledge cycle is allowed to be performed. cycle clock second begin concurrent operations execution sequence with no memory data access: execution sequence with memory data access: cycle clock first end of fetch decode decode operations concurrent pclk memory data read or write perform internal operations and alu operations, as required cycle clock first end of cycle clock second begin cycle clock first begin asic bus operations second clock cycle end of cycle clock first begin address of memory location is placed onto ma19-ma01 bus place address of next instruction onto ma19-ma01 fetch next instruction perform alu operations instruction latches into address of next instruction is placed onto ma19-ma01 bus instruction latches ir into ir figure 10. instruction execution sequence top top top top next ext next top next next ir ir cr hs-rtx2010rh
12 : the program counter register contains the address of the next instruction to be fetched from main memory. at reset, the contents of are set to 0. : the index register contains 16 bits of the 21-bit top element of the return stack, and is also used to hold the count for streamed and loop instructions (see figure 19). in addition, can be used to hold data and can be written from . the contents of may be accessed in either the push/pop mode in which values are moved to/from stack memory as required, or in the read/write mode in which the stack memory is not affected. the asic address used for determines what type of operation will be performed (see table 5). when the streamed instruction mode (see rtx programmers reference manual) is used, a count is written to and the next instruction is executed that number of times plus one (i.e., count + 1). : the multi-step divide register holds the divisor during step divide operations, while the 32-bit dividend is in and . may also be used as a general purpose scratch pad register. : the square root register holds the intermediate values used during step square root calculations. may also be used as a general purpose scratch pad register. on-chip peripheral registers the hs-rtx2010rh has an on-chip interrupt controller, a memory page controller, two stack controllers, three timer/counters, a multiplier-accumulator, a barrel shifter, and a leading zero detector. each of these peripherals utilizes on-chip registers to perform its functions. timer/counter registers , , : the timer/counter registers are 16-bit read-only registers which contain the current count value for each of the three timer/counters. the counter is decremented at each rising clock edge of tclk. reading from these registers at any time does not disturb their contents. the sequence of timer/counter operations is shown in figure 23 in the timer/counters section. , , : the timer preload registers are write-only registers which contain the initial 16-bit count values which are written to each timer. after a timer counts down to zero, the preload register for that timer reloads its initial count value to that timer register at the next rising clock edge, synchronously with tclk. writing to these registers causes the count to be loaded into the corresponding timer/ counter register on the following cycle. multiplier-accumulator (mac) registers: : the multiplier high product register holds the most signi?ant 16 bits of the 32-bit product generated by the rtx multiplier. if the registers round bit is set, this register contains the rounded 16-bit output of the multiplier. in the accumulator context, this register holds the middle 16 bits of the mac. : the multiplier lower product register holds the least signi?ant 16 bits of the 32-bit product generated by the rtx multiplier. it is also the register which holds the least signi?ant 16 bits of the mac accumulator. : the mac extension register holds the most significant 16 bits of the mac accumulator. when using the barrel shifter, this register holds the shift count. when using the leading zero detector, the leading zero count is stored in this register. interrupt controller registers : the interrupt vector register is a read-only register which holds the current interrupt vector value. see figure 12 and table 4. : the interrupt base/control register is used to store the interrupt vector base address and to specify con?uration information for the processor, as indicated by the bit assignments in figure 13. r/w; carry r/w; complex carry set interrupt disable; 0 = int. enabled; 1 = int. disabled write - only (reads as 0); r/w; byte order bit 0 = addressing mode 0 1 = addressing mode 1 resets to 0. modes: reserved (note) r/w; boot drives output signal to select boot rom; interrupt latch read only; disable status read only; interrupt arce; asic read cycle extend when set extends cycle on nmi mode 1 = return from nmi possible 0 = no return from nmi reserved (note) external asic reads (rtx 2000 mode) cr 5 6 7 80 1 2 3 4 9 11 1 11 1 5432 10 note: always read as ?? should be set = 0 during write operations. figure 11. bit assignments cr pc pc i i top i i i md top ext md sr sr tc0 tc1 tc2 tp0 tp1 tp2 mhr ibc mlr mxr ivr all zeros vector address (see table 1) 0 1 2 3 4 5 6 7 11 8 9 10 12 13 14 15 ivr bit 10 bit 11 bit 12 bit 15 bit 14 bit 13 ibc ibc ibc ibc ibc ibc ma15-ma00 ibc figure 12. bit assignments ivr ibc hs-rtx2010rh
13 : the interrupt mask register has a bit assigned for each maskable interrupt which can occur. when a bit is set, the interrupt corresponding to that bit will be masked. only the non-maskable interrupt (nmi) cannot be masked. see figure 14 for bit assignments for this register. stack controller registers : the stack pointer register holds the stack pointer value for each stack. bits 0-7 represent the next available stack memory location for the parameter stack, while bits 8- 15 represent the next available stack memory location for the return stack. these stack pointer values must be accessed together, as . see figure 15. : the stack over?w limit register is a write-only register which holds the over?w limit values (0 to 255) for the parameter stack (bits 0-7) and the return stack (bits 8-15). these values must be written together. see figure 16. : the stack under?w limit register holds the under?w limit values for the parameter stack and the return stack. in addition, this register is utilized to de?e the use of substacks for both stacks. these values must be accessed together. see figure 17. 0 1 2 3 4 5 6 7 8 9 1514 12 13 10 read-only; fatal stack error flag read-only; parameter stack underflow flag read-only; parameter stack overflow flag read-only; return stack underflow flag read-only; return stack overflow flag svr ibc parameter stack return stack fatal error dprsel: selects = 1: select = 0: select page register for data memory access sur cpr dpr round: multiplier control bit; selects rounding of 16 x 16 bit multiplication = 1: rounded 16-bit product = 0: unrounded 32-bit product input signals: tclk or ei5 - ei3 (table 6) select timer/counter cycext: allows extended cycle length for user memory instruction cycles; see clock and wait timing diagrams ma14 ma15 ma12 ma13 ma10 ma11 interrupt vector interrupt section) base (see the 11 fatal error figure 13. bit assignments ibc imr rsv, return stack overflow psv, parameter stack overflow rsu, return stack underflow psu, parameter stack underflow ei1 (external input pin) ei2 tci 0 tci 1 tci 2 ei3 ei4 ei5 swi imr 15 14 12 13 8 9 10 11 0 1 2 3 4 5 6 7 reserved (note) reserved (note) note: always read as ?? should be set = 0 during write operations. figure 14. bit assignments imr spr spr svr sur 8 9 psp, parameter stack pointer rsp, return stack pointer 0 1 2 3 4 5 6 7 spr 10 11 15 14 1312 figure 15. bit assignments spr pvl: parameter stack overflow limit. rvl: return stack overflow limit. svr 0 1 2 3 4 5 6 7 8 9 1 4 1 5 1 3 1 2 1 1 1 0 number of words from top of current substack number of words from top of current substack figure 16. bit assignments svr hs-rtx2010rh
14 memory page controller registers : the code page register contains the value for the current 32k-word code page. see figure 18 for bit ?ld assignments. : the index page register extends the index register ( ) by 5 bits; i.e., when a subroutine return is performed, the contains the code page from which the subroutine was called, and comprises the 5 most signi?ant bits of the top element of the return stack. see figure 19. during nonsubroutine operation, writing to causes the current code page value to be written to . reading or writing directly to does not push the return stack. : the data page register contains the value for the current 32k-word data page. see figure 20 for bit ?ld assignments. : the user page register contains the value for the current user page. see figure 21 for bit ?ld assignments. : the user base address register contains the base address for user memory instructions. see figure 21 for bit ?ld assignments. 0 1 2 3 4 5 6 7 8 9 psf: parameter stack start flag psu: parameter 0 - 31 words from bottom of substack stack underflow limit rsf: return stack start flag rsu: return stack 0 - 31 words from bottom of substack underflow limit return substack bits: = 00: eight 32 word stacks = 01: four 64 word stacks sur 1 5 1 4 13 12 11 10 parameter substack bits: = 00: eight 32 word stacks = 01: four 64 word stacks = 10: two 128 word stacks = 11: one 256 word stack = 10: two 128 word stacks = 11: one 256 word stack figure 17. bit assignments sur cpr 0 1 2 3 4 5 6 7 11 8 9 10 12 13 14 15 cpr ma16 ma17 ma18 ma19 reserved (note) note: always read as ?? should be set = 0 during write operations. figure 18. bit assignments cpr ipr i ipr i ipr ipr dpr upr ubr bit assignments during non-subroutine operations i ipr 9 0 1 2 3 4 5 6 7 8 bit assignments during subroutine operations defines return address type of return = 1: interrupt returns: = 0: subroutine returns: stored during interrupt where dprsel bit is or subroutine call i ipr 9 0 1 2 3 4 5 6 7 8 used for temporary storage of variables, loop counts, and stream counts current code page value 0 29 18 17 16 15 14 13 12 11 10 1 0 29 18 17 16 15 14 13 12 11 10 1 figure 19. and bit assignments i ipr 0 1 2 3 4 5 6 7 11 8 9 10 12 13 14 15 dpr ma16 ma17 ma18 ma19 reserved (note) note: always read as ?? should be set = 0 during write operations. figure 20. bit assignments dpr 0 1 2 3 4 5 6 7 11 8 9 10 12 13 14 15 user page register ubr ma15 - ma06 0 1 2 3 4 5 6 7 11 8 9 10 12 13 14 15 i r 0 1 2 3 4 5 6 7 11 8 9 10 12 13 14 15 upr ma19 ma18 ma17 ma16 not used to generate this address instruction register reserved user base register address reserved ma05 ma04 ma03 ma02 ma01 (note) (note) note: always read as ?? should be set = 0 during write operations. figure 21. and bit assignments upr ubr hs-rtx2010rh
15 initialization of registers initialization of the on-chip registers occurs when a high level on the rtx reset pin is held for a period of greater than or equal to four rising edges of iclk plus 1/2 iclk cycle setup and hold times. while the reset input is high, the tclk and pclk clock outputs are held reset in the low state. table 1 shows initialization values and asic addresses for the on-chip registers. as indicated, both the and the are cleared and execution begins at page 0, word 0 when the processor is reset. the reset has a schmitt trigger input, which allows the use of a simple rc network for generation of a power-on reset signal. this helps to minimize the circuit board space required for the reset circuit. to ensure reliable operation even in noisy embedded control environments, the reset input is ?tered to prevent a reset caused by a glitch of less than four iclk cycles duration. pc cpr table 1. register initialization and asic address assignments register hex addr initialized contents description/comments 0000 0000 0000 0000 top register 1111 1111 1111 1111 next register 0000 0000 0000 0000 instruction register 00h 01h 02h 1111 1111 1111 1111 index register 03h 0100 0000 0000 1000 configuration register: boot = 1; interrupts disabled; byte order = 0. 04h 1111 1111 1111 1111 multi-step divide register 06h 0000 0010 0000 0000 square root register 07h 0000 0000 0000 0000 program counter register 08h 0000 0000 0000 0000 interrupt mask register 09h 0000 0000 0000 0000 stack pointer register: the beginning address for each stack is set to a value of ?? 0ah 0000 0111 0000 0111 stack underflow limit register 0bh 0000 0010 0000 0000 interrupt vector register: read only; this register holds the current interrupt vector value, and is initialized to the ?o interrupt?value. 0bh 1111 1111 1111 1111 stack overflow limit register: write-only; each stack limit is set to its maximum value. 0ch 0000 0000 0000 0000 index page register 0dh 0000 0000 0000 0000 data page register: the data address page is set for page ?? 0eh 0000 0000 0000 0000 user page register: the user address page is set for page ?? 0fh 0000 0000 0000 0000 code page register: the code address page is set for page ?? 10h 0000 0000 0000 0000 interrupt base/control register 11h 0000 0000 0000 0000 user base address register: the user base address is set to ? within the user page. 12h 0000 0000 0000 0000 mac extension register / 13h 0000 0000 0000 0000 timer/counter register 0: set to time out after 65536 clock periods or events. / 14h 0000 0000 0000 0000 timer/counter register 1: set to time out after 65536 clock periods or events. / 15h 0000 0000 0000 0000 timer/counter register 2: set to time out after 65536 clock periods or events. 16h 0000 0000 0000 0000 multiplier lower product register 17h 0000 0000 0000 0000 multiplier high product register top next ir i cr md sr pc imr spr sur ivr svr ipr dpr upr cpr ibc ubr mxr tc0 tp0 tc1 tp1 tc2 tp2 mlr mhr hs-rtx2010rh
16 dual stack architecture the hs-rtx2010rh features a dual stack architecture. the two 256-word stacks are the parameter stack and the return stack, both of which may be accessed in parallel by a single instruction, and which minimize overhead in passing parameters between subroutines. the functional structure of each of these stacks is shown in figure 22. the parameter stack is used for temporary storage of data and for passing parameters between subroutines. the top two elements of this stack are contained in the and registers of the processor, and the remainder of this stack is located in stack memory. the stack memory assigned to the parameter stack is 256 words deep by 16 bits wide. the return stack is used for storing return addresses when performing subroutine calls, or for storing values temporarily. because the hs-rtx2010rh uses a separate return stack, it can call and return from subroutines and interrupts with a minimum of overhead. the return stack is 21 bits wide. the 16-bit index register, , and the 5-bit index page register, , hold the top element of this stack, while the remaining elements are located in stack memory. the stack memory portion of the return stack is 21 bits wide, by 256 words deep. the data on the return stack takes on different meaning, depending upon whether the return stack is being used for temporary storage of data or to hold a return address during a subroutine operation (figure 19). hs-rtx2010rh stack controllers the two stacks of the hs-rtx2010rh are controlled by identical programmable stack controllers. the operation of the programmable stack controllers depends on the contents of three registers. these registers are , the stack pointer register, , the stack over?w limit register, and , the stack under?w limit register (see figures 15, 16, and 17). contains the address of the next stack memory location to be accessed in a stack push (write) operation. after a push, the is incremented (post-increment operation). in a stack pop (read) operation, the stack memory location with an address one less than the will be accessed, and then the will be decremented (pre-decrement operation). at start-up, the ?st stack location to have data pushed into it is location zero. upper and lower limit values for the stacks are set into the stack over?w limit register and in the stack under?w limit register. these values allow interrupts to be generated prior to the occurrence of stack over?w or under?w error conditions (see section on stack error conditions for more detail). since the hs-rtx2010rh can take up to four clock cycles to respond to an interrupt, the values set in these registers should include a safety margin which allows valid stack operation until the processor executes the interrupt service routine. top next i ipr spr svr sur spr spr spr spr (on-chip) stack memory parameter stack 8 9 10 11 12 0 75 61 2 3 4 13 14 15 8 9 10 11 12 0 75 61 2 3 4 13 14 15 return stack (on-chip) stack memory rvl pvl rsu rsp 1 28 9 010 2 3 4 5 6 7 3 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 0 1 2 i ipr psu psp top next 8 9 10 11 12 13 14 15 0 75 61 2 3 4 svr 8 9 10 11 12 13 14 15 0 75 61 2 3 4 spr 8 9 10 11 12 13 14 15 0 75 61 2 3 4 sur figure 22. dual stack architecture hs-rtx2010rh
17 substacks each 256-word stack may be subdivided into up to eight 32 word substacks, four 64 word substacks, or two 128 word substacks. this is accomplished under hardware control for simpli?d management of multiple tasks. stack size is selected by writing to bits 1 and 2 of the for the parameter stack, and bits 9 and 10 for the return stack. substacks are implemented by making bits 5-7 of the (for the parameter stack) and bits 13-15 of the (for the return stack) control bits. for example, if there were eight 32 word substacks implemented in the parameter stack, bits 5-7 of the are not incremented, but instead are used as an offset pointer into the parameter stack to indicate the beginning point (i.e., sub stack number) of each 32 word substack implemented. because of this, a particular substack is selected by writing a value which contains both the stack pointer value and the substack number to the . each stack has a stack start flag (psf and rsf) which may be used for implementing virtual stacks. for the parameter stack, the start flag is bit zero of the , and for the return stack it is bit eight. if the stack start flag is one, the stack starts at the bottom of the stack or substack (location 0). if the stack start flag is zero, the substack starts in the middle of the stack. an exception to this occurs if the over?w limit in is set for a location below the middle of the stack. in this case, the stacks always start at the bottom locations. see table 2 for the possible stack con?urations. manipulating the stack start flag provides a mechanism for creating a virtual stack in memory which is maintained by interrupt driven handlers. possible applications for substacks include use as a recirculating buffer (to allow quick access for a series of repeated values such as coef?ients for polynomial evaluation or a digital ?ter), or to log a continuous stream of data until a triggering event (for analysis of data before and after the trigger without having to store all of the incoming data). the latter application could be used in a digital oscilloscope or logic analyzer. stack error conditions stack errors include over?w, under?w, and fatal errors. over?ws occur when an attempt is made to push data onto a full stack. since the stacks wrap around, the result is that existing data on the stack will be overwritten by the new data when an over?w occurs. under?ws occur when an attempt is made to pop data off an empty stack, causing invalid data to be read from the stack. in both cases, a buffer zone may be set up by initializing and so that stack error interrupts are generated prior to an actual over?w or under?w. the limits may be determined from the contents of and using table 2. the state of all stack errors may be determined by examining the ?e least signi?ant bits of , where the stack error ?gs may be read but not written to. all stack error ?gs are cleared whenever a new value is written to . fatal stack error: each stack can also experience a fatal stack error. this error condition occurs when an attempt is made to push data onto or to pop data off of the highest location of the substack. it does not generate an interrupt (since the normal stack limits can be used to generate the interrupt). the fatal errors for the stacks are logically or?d together to produce bit 0 of the interrupt base control register, and they are cleared whenever is written to. the implication of a fatal error is that data on the stack may have been corrupted or that invalid data may have been read from the stack. hs-rtx2010rh timer/counters the hs-rtx2010rh has three 16-bit timers, each of which can be con?ured to perform timing or event counting. all decrement synchronously with the rising edge of tclk. timer registers are readable in a single machine cycle. the timer selection bits of the determine whether a timer is to be con?ured for external event counting or internal time-base timing. this con?ures the respective counter clock inputs to the on-chip tclk signal for internal timing, or to the ei5 - ei3 input pins for external signal event counting. ei5, ei4, and ei3 are synchronized internally with tclk. see table 3 for timer/clock selection by bit values. the timers ( , and ) are all free-running, and when they time out, they reload automatically with the programmed initial value from their respective timer pre load registers ( , , and ), then continue timing or counting. each timer provides an output to the interrupt controller to indicate when a time-out for the timer has occurred. the hs-rtx2010rh can determine the state of a timer at any time either by reading the timers value, or upon a time- out by using the timers interrupt (see the interrupt controller section for more information about how timer interrupts are handled). figure 23 shows the sequence of timer/counter operations. sur spr spr spr spr sur svr svr sur svr sur ibc spr spr ibc ibc tc0 tc1 tc2 tpo tc0 tp1 tc1 tp2 tc2 hs-rtx2010rh
18 table 2. stack/substack configurations for given control bit settings control bit settings parameter stack configuration svr sur stack size words stack range lowest address highest address v7v6v5v4u2u1u0 7654321076543210 xxx000x 32 p7p6p500000p7p6p511111 xxx1000 32 p7p6p500000p7p6p511111 xxx1001 32 p7p6p500000p7p6p511111 xx0x01x 64 p7p6000000p7p6111111 xx1x010 64 p7p6000000p7p6111111 xx1x011 64 p7p6000000p7p6111111 x0xx10x 128 p70000000p71111111 x1xx100 128 p70000000p71111111 x1xx101 128 p70000000p71111111 0xxx11x 256 0000000011111111 1xxx110 256 0000000011111111 1xxx111 256 0000000011111111 control bit settings return stack configuration svr sur stack size words stack range lowest address highest address v15v14v13v12u10u9u8 7654321076543210 xxx000x 32 p15p14p1300000p15p14p1311111 xxx1000 32 p15p14p1300000p15p14p1311111 xxx1001 32 p15p14p1300000p15p14p1311111 xx0x01x 64 p15p14000000p15p14111111 xx1x010 64 p15p14000000p15p14111111 xx1x011 64 p15p14000000p15p14111111 x0xx10x 128 p150000000p151111111 x1xx100 128 p150000000p151111111 x1xx101 128 p150000000p151111111 0xxx11x 256 0000000011111111 1xxx110 256 0000000011111111 1xxx111 256 0000000011111111 hs-rtx2010rh
19 table 2. stack/substack configurations for given control bit settings (continued) control bit settings parameter stack configuration svr sur fatal limit underflow limit overflow limit v7v6v5v4u2u1u0765432107654321076543210 x x x 0 0 0 x p7 p6 p5 1 1 1 1 1 p7 p6 p5 0 u6 u5 u4 u3 p7 p6 p5 0 v3 v2 v1 v0 x x x 1 0 0 0 p7 p6 p5 0 1 1 1 1 p7 p6 p5 1 u6 u5 u4 u3 p7 p6 p5 0 v3 v2 v1 v0 x x x 1 0 0 1 p7 p6 p5 1 1 1 1 1 p7 p6 p5 0 u6 u5 u4 u3 p7 p6 p5 1 v3 v2 v1 v0 x x 0 x 0 1 x p7 p6 1 1 1 1 1 1 p7 p6 0 u7 u6 u5 u4 u3 p7 p6 0 v4 v3 v2 v1 v0 x x 1 x 0 1 0 p7 p6 0 1 1 1 1 1 p7 p6 1 u7 u6 u5 u4 u3 p7 p6 0 v4 v3 v2 v1 v0 x x 1 x 0 1 1 p7 p6 1 1 1 1 1 1 p7 p6 0 u7 u6 u5 u4 u3 p7 p6 1 v4 v3 v2 v1 v0 x0xx10xp71111111p700u7u6u5u4u3p70v5v4v3v2v1v0 x1xx100p70111111p710u7u6u5u4u3p70v5v4v3v2v1v0 x1xx101p71111111p700u7u6u5u4u3p71v5v4v3v2v1v0 0xxx11x11111111000u7u6u5u4u30v6v5v4v3v2v1v0 1xxx11001111111100u7u6u5u4u30v6v5v4v3v2v1v0 1xxx11111111111000u7u6u5u4u31v6v5v4v3v2v1v0 control bit setting parameter stack configuration svr sur fatal limit underflow limit overflow limit v15v14v13v12u10u9u8765432107654321076543210 x x x 0 0 0 x p15 p14 p13 1 1 1 1 1 p15 p14 p13 0 u14 u13 u12 u11 p15 p14 p13 0 v11 v10 v9 v8 x x x 1 0 0 0 p15 p14 p13 0 1 1 1 1 p15 p14 p13 1 u14 u13 u12 u11 p15 p14 p13 0 v11 v10 v9 v8 x x x 1 0 0 1 p15 p14 p13 1 1 1 1 1 p15 p14 p13 0 u14 u13 u12 u11 p15 p14 p13 1 v11 v10 v9 v8 x x 0 x 0 1 x p15 p14 1 1 1 1 1 1 p15 p14 0 u15 u14 u13 u12 u11 p15 p14 0 v12 v11 v10 v9 v8 x x 1 x 0 1 0 p15 p14 0 1 1 1 1 1 p15 p14 1 u15 u14 u13 u12 u11 p15 p14 0 v12 v11 v10 v9 v8 x x 1 x 0 1 1 p15 p14 1 1 1 1 1 1 p15 p14 0 u15 u14 u13 u12 u11 p15 p14 1 v12 v11 v10 v9 v8 hs-rtx2010rh
20 control bit setting parameter stack configuration svr sur fatal limit underflow limit overflow limit v15v14v13v12u10u9u8765432107654321076543210 x0xx10xp151111111p1500u15u14u13u12u11p150v13v12v11v10v9v8 x1xx100p150111111p1510u15u14u13u12u11p150v13v12v11v10v9v8 x1xx101p151111111p1500u15u14u13u12u11p151v13v12v11v10v9v8 0xxx11x11111111000u15u14u13u12u110v14v13v12v11v10v9v8 1xxx11001111111100u15u14u13u12u110v14v13v12v11v10v9v8 1xxx11111111111000u15u14u13u12u111v14v13v12v11v10v9v8 notes: 18. : stack pointer register, : stack overflow register, : stack underflow register. 19. p0 . . p15: bits, v0 . . v15: bits, u0 . . u15: bits. 20. the overflow limit is the stack memory address at which an overflow condition will occur during a stack write operation. 21. the underflow limit is the stack memory address below which an underflow condition will occur during a stack read operation. 22. the fatal limit is the stack memory address at which a fatal error condition will occur during a stack read or write operati on. 23. stack error conditions remain in effect until a new value is written to the . 24. stacks and sub-stacks are circular: after writing to the highest location in the stack, the next location to be written to will be the lowest locatio n; after reading the lowest location, the highest location will be read next. table 2. stack/substack configurations for given control bit settings (continued) spr svr sur spr svr sur spr hs-rtx2010rh
21 hs-rtx2010rh interrupt controller the hs-rtx2010rh interrupt controller manages interrupts for the hs-rtx2010rh microcontroller core. its sources include two on-chip peripherals and six external interrupt inputs. the two classes of on-chip peripherals that produce interrupts are the stack controllers and the timer/counters. interrupt controller operation when one of the interrupt sources requests an interrupt, the interrupt controller checks whether the interrupt is masked in the interrupt mask register. if it is not, the controller attempts to interrupt the processor. if processor interrupts are enabled (bit 4 of the con?uration register), the processor will execute an interrupt acknowledge cycle, during which it disables interrupts to ensure proper completion of the inta cycle. in response to the interrupt acknowledge cycle, the interrupt controller places an interrupt vector on the internal asic bus, based on the highest priority pending interrupt. the processor performs a special subroutine call to the address in memory page 0 contained in the vector. this special subroutine call is different in that it saves a status bit on the return stack indicating the call was caused by an interrupt. thus, when the interrupt handler executes a subroutine return, the processor knows to automatically re-enable interrupts. before the interrupt handler returns, it must ensure that the condition that caused the interrupt is cleared. otherwise the processor will again be interrupted immediately upon its return. processor interrupts are enabled and disabled by clearing and setting the interrupt disable flag. when the rtx is reset, this ?g is set (bit 04 of the = 1), disabling the interrupts. this bit is a write-only bit that always reads as 0, allowing interrupts to be enabled in only 2 cycles with a simple read/write operation in which the processor reads the bit value, then writes it back to the same location. the actual status of the interrupt disable flag can be read from bit 14 of . asic bus activate timeout interrupt activate timeout interrupt activate timeout interrupt execute count execute count execute count interrupt reset interrupt reset interrupt reset interrupt controller preload register tp2 inta cycle or asic read command load tc0 rising edge tclk rising edge tclk register preload register tp0 timer/counter timer/counter load tc1 timer/counter load tc2 preload register tp1 top figure 23. hs-rtx2010rh timer/counter operation table 3. timer/counter bit values timer clock source bit 09 bit 08 0 0 tclk tclk tclk 0 1 tclk tclk ei3 1 0 tclk ei4 ei3 1 1 ei5 ei4 ei3 ibc tc2 tc1 tc0 cr cr hs-rtx2010rh
22 during read and write operations to the con?uration register, ( ), interrupts are inhibited to allow the program to save and restore the state of the interrupt enable bit. in addition to disabling interrupts at the processor level, all interrupts except the non-maskable interrupt (nmi) can be individually masked by the interrupt controller by setting the appropriate bit in the interrupt mask register ( ). resetting the hs-rtx2010rh causes all bits in the to be cleared, thereby unmasking all interrupts. the nmi on the hs-rtx2010rh has two modes of operation which are controlled by the nmi_mode flag (bit 11 of the ). when this bit is cleared (0), the nmi can not be masked, and can interrupt any cycle. this allows a fast response to the nmi, but may not allow a return from interrupt to operate correctly. nmi_mode is cleared when the processor is reset. when nmi_mode is set (1), a return from the nmi service routine will result in the processor continuing execution in the state it was in when it was interrupted. when in this second mode nmi may be inhibited by the processor during certain critical operations (see interrupt suppression), and may, therefore, not be serviced as quickly as in the first mode of operation. when servicing an nmi_mode set to 1, further nmis and maskable interrupts are disabled until the nmi interrupt service routine has completed, and a return from interrupt has been executed. the interrupt controller prioritizes interrupt requests and generates an interrupt vector for the highest priority interrupt request. the address that the vector points to is determined by the source of the interrupt and the contents of the interrupt base/control register ( ). see figure 12 for the interrupt vector register bit assignments. because address bits ma19-ma16 are always zero in an interrupt acknowledge cycle, the entry point to the interrupt handlers must reside on memory page zero. because address bits ma04-ma01 are always zero in an interrupt acknowledge cycle, interrupt vectors are 32 bytes apart. this means that interrupt handler routines that are 32 bytes or less can be compiled directly into the interrupt table. interrupt handlers greater than 32 bytes must be compiled separately and called from the interrupt table. the rest of the vector is generated as indicated in table 1. to guarantee that the interrupt vector will be stable during an inta cycle, the interrupt controller inhibits the generation of a new interrupt vector while inta is high, and will not begin generating a new interrupt vector on either edge of inta. the interrupt vector can also be read from the interrupt vector register ( ) directly. this allows interrupt requests to be monitored by software, even if they are disabled by the processor. if no interrupts are being requested, bit 09 of the will be 1. external interrupts ei5-ei1 are active high level-sensitive inputs. (note: when used as timer/counter inputs, ei5-ei3 are edge sensitive). therefore, the interrupt handlers for these interrupts must clear the source of interrupt prior to returning to the interrupted code. the external nmi, however, is an edge-sensitive input which requires a rising edge to request an interrupt. the nmi input also has a glitch filter circuit which requires that the signal that initiates the nmi must last at least two rising and two falling edges of iclk. finally, a mechanism is provided by which an interrupt can be requested by using a software command. the software interrupt (swi) is requested by executing an instruction that will set an internal ?p-?p attached to one input of the table 4. interrupt sources, priorities and vectors priority interrupt source sensitivity bit vector address bits 09 08 07 06 05 0 (high) nmi non-maskable interrupt pos edge n/a 0 1 1 1 1 1 ei1 external interrupt 1 high level 01 0 1 1 1 0 2 psu parameter stack underflow high level 02 0 1 1 0 1 3 rsu return stack underflow high level 03 0 1 1 0 0 4 psv parameter stack overflow high level 04 0 1 0 1 1 5 rsv return stack overflow high level 05 0 1 0 1 0 6 ei2 external interrupt 2 high level 06 0 1 0 0 1 7 tci0 timer/counter 0 edge 07 0 1 0 0 0 8 tci1 timer/counter 1 edge 08 0 0 1 1 1 9 tci2 timer/counter 2 edge 09 0 0 1 1 0 10 ei3 external interrupt 3 high level 10 0 0 1 0 1 11 ei4 external interrupt 4 high level 11 0 0 1 0 0 12 ei5 external interrupt 5 high level 12 0 0 0 1 1 13 (low) swi software interrupt high level 13 0 0 0 1 0 n/a none no interrupt n/a n/a 1 0 0 0 0 imr cr imr imr cr ibc ivr ivr hs-rtx2010rh
23 interrupt controller. the swi is reset by executing an instruction that clears the ?p-?p. the ?p-?p is accessed by i/o reads and writes. because the swi interrupt may not be serviced immediately, the instructions which immediately follow the swi instruction should not depend on whether or not the interrupt has been serviced, and should cause a one or two-cycle idle condition (typically, this is done with one or two nop instructions). if an interrupt condition occurs, but ?oes away?before the processor has a chance to service it, a ?o interrupt vector is generated. a ?o interrupt?vector is also generated if an interrupt acknowledge cycle takes less than two cycles to execute and no other interrupt conditions need to be serviced. to prevent unforeseen errors, it is recommended that valid code be supplied at every interrupt vector location, including the ?o interrupt?vector, which should always be initialized with valid code. it is recommended that interrupt handlers save and restore the contents of . interrupt suppression the hs-rtx2010rh allows maskable interrupts and mode 1 nmis (the nmi_mode flag in bit 11 of the is set) to be suppressed, delaying them temporarily while critical operations are in progress. critical operations are instruction sequences and hardware operations that, if interrupted, would result in the loss of data or misoperation of the hardware. (note: only the processor may suppress nmis.) standard critical operations during which interrupts are automatically suppressed by the processor include streamed instructions (see the description of the register), long call sequences (see ?ubroutine calls and returns?, and loading . in addition to this, external devices can also suppress maskable interrupts during critical operations by applying a high level on the intsup pin for as long as required. since the mode 0 nmi (the nmi_mode flag in bit 11 of the is cleared) can cause the processor to perform an interrupt acknowledge cycle in the middle of these critical operations, thereby preventing a normal return to the interrupted instruction, a subroutine return should be used with care from a mode 0 nmi service routine. the mode 0 nmi should be used only to indicate critical system errors, and the mode 0 nmi handler should re-initialize the system. interrupts which have occurred while interrupt suppression is in effect will be recognized on a priority basis as soon as the suppression terminates, provided the condition which generated the interrupt still exists. stack error interrupts the stack controllers request an interrupt whenever a stack over?w or under?w condition exists. these interrupts can be cleared by rewriting . see the section on ?ual stack architecture?for more information regarding how the limits set into and are used. stack over?w: a stack over?w occurs when data is pushed onto the stack location pointed to by the , as determined in table 5. after the processor is reset, this is location 255 in either the parameter stack or return stack. a stack over?w interrupt request stays in effect until cleared by writing a new value to the . in addition to generating an interrupt, the state of the stack over?w ?gs may be read out of the , bit 3 for the parameter stack, and bit 4 for the return stack. see figures 13, 15 and 16. stack under?w: the stack under?w limit occurs when data is popped off the stack location immediately below that pointed to by the , as determined in table 2. the state of the stack under?w error ?gs may be read out of bits 1 and 2 of the for the parameter and return stacks respectively. in the reset state of the , an under?w will be generated at the same time that a fatal error is detected. an under?w buffer region can be set up by selecting an under?w limit greater than zero by writing the corresponding value into the . the stack under?w interrupt request stays in effect until a new value is written into the , at which time it is cleared. timer/counter interrupts the timers generate edge-sensitive interrupts whenever they are decremented to 0. because they are edge-sensitive and are cleared during an interrupt acknowledge cycle or during the direct reading of by software, no action is required by the handlers to clear the interrupt request. the hs-rtx2010rh alu the hs-rtx2010rh has a 16-bit alu capable of performing standard arithmetic and logic operations: add and subtract (a-b and b-a; with and without carry) and, or, xor, nor, nand, xnor, not the and registers can also undergo single bit shifts in the same cycle as a logic or arithmetic operation. in figure 24, the control and data paths to the alu are shown. except for and , each of the internal core registers can be addressed explicitly, as can other internal registers in special operations such as in step instructions. in each of these cases, the input would be addressed as a device on the asic bus. when executing these instructions, the arithmetic/logic operand (a) starts out in and is placed on the t-bus. operand (b) arrives at the alu on the y-bus, but can come from one of the following four sources: ; an internal register; an asic bus device; or from the 5 least signi?ant bits of . the source of operand (b) is determined by the instruction code in . the result of the alu operation is placed into . cr cr i cr cr spr ibc sur svr spr ibc sur ibc sur sur spr ivr top next top next top next ir ir top hs-rtx2010rh
24 step arithmetic instructions which are performed through the alu are divide and square root. execution of each step of the arithmetic operation takes one cycle, a 32/16-bit step divide takes 21 cycles, and a 32/16-bit step square root takes 25 cycles. sign and scaling functions are controlled by the alu function and shift options, which are part of the coded instruction contained in . see table 20 and table 21 and the programmers reference manual for details. unsigned step divide operation assumes a double precision (32-bit) dividend, with the most signi?ant word placed in , the less signi?ant word in , and the divisor in . in each step, if the contents in are equal to or greater than the contents in (and therefore no borrow is generated), then the contents of are subtracted from the contents of . the result of the subtraction is placed into . the contents of and are then jointly shifted left one bit (32-bit left shift), where the value shifted into the least signi?ant bit of is the value of the borrow bit on the ?st pass, or the value of the complex carry bit on each of the subsequent passes. on the 15th and ?al pass, only is shifted left, receiving the value of the complex carry bit into the lsb. is not shifted. the ?al result leaves the quotient in , and the remainder in . during a step square root operation, the 32-bit argument is assumed to be in and , as in the step divide operation. the ?st step begins with containing zeros. the step square root is performed much like the step divide, except that the input from the y-bus is the logical or of the contents of and the value in shifted one place to the left (2* ). when the subtraction is performed, is or?d into , and is shifted one place to the right. at the end of the operation, the square root of the original value is in and , and the remainder is in . hs-rtx2010rh floating point/dsp on chip peripherals the hs-rtx2010rh multiplier-accumulator the hardware multiplier-accumulator (mac) on the hs-rtx2010rh functions as both a multiplier, and a multiplier- accumulator. when used as a multiplier alone, it multiplies two 16-bit numbers, yielding a 32-bit product in one clock cycle. when used as a multiplier-accumulator, it multiplies two 16-bit numbers, yielding an intermediate 32-bit product, which is then added to the 48-bit accumulator. this entire process takes place in a single clock cycle. the multiplier-accumulator functions are activated by i\o read and write instructions to asic bus addresses assigned to the mac. the macs input operands come from three possible sources (see figure 25): 1. the and registers. 2. the parameter (data) stack and memory via (streamed mode only - see the programmers reference manual). 3. memory via and an input from the asic bus (streamed mode only - see the programmers reference manual). operand (a) y-bus t- b u s alu program memory select operand (b) top shifter alu control yt 5 least significant bits asic bus device internal registers next decode i r i r note: data paths are represented by solid lines; control paths are represented by dashed lines. figure 24. alu operations-control paths and data flow ir top next md top md md top top top next next next top ext top top next md sr md md sr md sr md next top top ext next ext hs-rtx2010rh
25 these inputs can be treated as either signed (twos complement) or unsigned integers, depending on the form of the instruction used. in addition, if the round option is selected, the multiplier can round the result to 16 bits. note that the mac instructions do not pop the parameter stack; the contents of and remain intact. for the multiplier, the product is read from the multiplier high product register, , which contains the upper 16 bits of the product, and the multiplier low product register, , which contains the lower 16 bits. for the multiplier- accumulator, the accumulated product is read from the multiplier extension register, , which contains the upper 16 bits, the , which contains the middle 16 bits, and the , which contains the low 16 bits. the registers may be read in any order, and there is no requirement that all registers be read. reading from any of the three registers moves its value into , and pushes the original value in into . if the read is from or , the original value of is lost, i.e. it is not pushed onto stack memory. this permits overwriting the original operands left in and , which are not popped by the mac operations. if the read is from , the original value of is pushed onto the stack. in addition to this, any of the three mac registers can be directly loaded from . this pops into and the parameter stack into . if 32-bit precision is not required, the multiplier output may be rounded to 16 bits. this is accomplished by setting the round bit in the interrupt base/control register, , to 1. if the round bit is set to 1, all operations that use the multiplier automatically round the least significant 16 bits of the result into the most significant 16 bits. the rounding is achieved by adding 8000h to the least significant 16 bits (during the same cycle as the multiply). thus, if the round bit is set: 1. if the most signi?ant bit of the is set (1), the is incremented. 2. if the most signi?ant bit of the is not set (0), the is left unchanged. the round bit functions independently of whether the signed or unsigned bit is used. the multiply instructions suppress interrupts during the multiplication cycle. reading , or also suppresses interrupts during the read. this allows a multiplication operation to be performed, and both the upper and lower registers to be read sequentially, with no danger of a non-nmi interrupt service routine corrupting the contents of the registers between reads. the multiply-accumulate instructions do not suppress interrupts during instruction execution. for additional information on the hs-rtx2010rh mac see the programmers reference manual. the hs-rtx2010rh on-chip barrel shifter and leading zero detector the hs-rtx2010rh has both a 32-bit barrel shifter and a 32-bit leading zero detector for added ?ating-point and dsp performance. the inputs to the barrel shifter and leading zero detector are the top two elements of the parameter stack, the and registers. the barrel shifter uses a 5-bit count stored in the register to determine the number of places to right or left shift the double word operand contained in the and registers. the output of the barrel shifter is stored in the and registers, with the top 16 bits in and the bottom 16 bits in . next sign ext. top mxr top mhr top mlr mhr mxr 16 16 data stack asic bus 5 32 mac 16 x 16 top 32-bit brl shifter 32-bit lzd register 48 figure 25. hs-rtx2010rh floating point/dsp logic top next mhr mlr mxr mhr mlr top top next mhr mlr next top next mxr next top next top next ibc mlr mhr mlr mhr mhr mlr top next mxr top next mhr mlr mhr mlr hs-rtx2010rh
26 the leading zero detector is used to normalize the double word operand contained in the and registers. the number of leading zeroes in the double word operand are counted, and the count stored in the register. the double word operand is then logically shifted left by this count, and the result stored in the and registers. again the upper 16 bits are in , and the lower 16 bits are in . this entire operation is done in one clock cycle with the normalize instruction. hs-rtx2010rh asic bus interface the hs-rtx2010rh asic bus services both internal processor core registers and the on-chip peripheral registers, and eight external off-chip asic bus locations. all asic bus operations require a single cycle to execute and transfer a full 16-bit word of data. the external asic bus maps into the last eight locations of the 32 location asic address space. the three least signi?ant bits of the address are available as the asic address bus. the addresses therefore map as shown in table 5. hs-rtx2010rh extended cycle operation the hs-rtx2010rh bus cycle operation can be optionally extended for two types of accesses: 1. user memory cycles 2. asic bus read operations the extension of normal hs-rtx2010rh bus cycle timing allows the interface of the processor to some peripherals, and slow memory devices, without using externally generated wait states. the bus cycle is extended by the same amount (1 tclk) as it would be if one wait state was added to the cycle, but the control signal timing is somewhat different (see timing diagrams). in a one wait state bus cycle, pclk is high for 1/2 tclk period, and low for 1-1/2 tclk periods (i.e., pclk is held low for one additional tclk period). in an extended cycle, pclk is high for 1 tclk period, and low for 1 tclk period (i.e., both the high and low portions of the pclk period are extended by 1/2 tclk period). setting the cycle extend bit (cycext), which is bit 7 of the register, will cause extended cycles to be used for all accesses to user memory. setting the asic read cycle extend bit (arce), which is bit 13 of the register, will cause extended cycles to be used for all read accesses on the external asic bus. both the cycext bit and the arce bit are cleared on reset. hs-rtx2010rh memory access the hs-rtx2010rh memory bus interface the hs-rtx2010rh can address 1 megabyte of memory, divided into 16 non-overlapping pages of 64k bytes. the memory page accessed depends on whether the memory access is for code (instructions and literals), data, user memory, or interrupt code. the page selected also depends on the contents of the page control registers: the code page register ( ), the data page register ( ), the user page register ( ), and the index page register ( ). furthermore, the user base address register ( ) and the interrupt base/control register ( ) are used to determine the complete address for user memory accesses and interrupt acknowledge cycles. external memory data is accessed through . when executing code other than an interrupt service routine, the memory page is determined by the contents of the . bits 03-00 generate address bits ma19-ma16, as shown in figure 18. the remainder of the address (ma15- ma01) comes from the program counter register ( ). after resetting the processor, both the and the are cleared and execution begins at page 0, word 0. a new code page is selected by writing a 4-bit value to the . the value for the code page is input to the through a preload procedure which withholds the value for one clock cycle before loading the to ensure that the next instruction is executed from the same code page as the instruction which set the new code page. execution immediately thereafter will continue with the next instruction in the new page. an interrupt acknowledge cycle is a special case of an instruction fetch cycle. when an interrupt acknowledge cycle occurs, the contents of the and are saved on the return stack and then the is cleared to point to page 0. the interrupt controller generates a 16-bit address, or ?ector? which points to the code to be executed to process the interrupt. to determine how the interrupt vector is formed, refer to figure 12 for the register bit assignments, and also to the interrupt controller section. the page for data access is provided by either or , as shown in figures 18 and 20. data memory access instructions can be used to access data in a memory page other than that containing the program code. this is done by writing the desired page number into the data page register ( ) and setting bit 5 (dprsel) of the table 5. asic bus map asic bus signal asic address ga02 ga01 ga00 000 18h 001 19h 010 1ah 011 1bh 100 1ch 101 1dh 110 1eh 111 1fh top ext mxr mhr mlr mhr mlr ibc cr cpr dpr upr ipr ubr ibc ext cpr pc pc cpr cpr cpr cpr cpr pc cpr cpr dpr dpr ibc hs-rtx2010rh
27 register to 1. if is set to equal , or if dprsel = 0, data will be accessed in the code page. the status of the dprsel bit is saved and restored as a result of a subroutine call or return. when the hs-rtx2010rh is reset, points to page 0 and dprsel resets to 0, selecting the . user memory consists of blocks of 32 words that can be located anywhere in memory. the word being accessed in a block is pointed to by the ?e least signi?ant bits of the user memory instruction (see table 17), eliminating the need to explicitly load an address into before reading or writing to the location. upon hs-rtx2010rh reset, is cleared and points to the block starting at word 0, while is cleared so that it points to page 0. the word in the block is pointed to by the ?e least signi?ant bits of the user memory instruction and bits 05-01 of the . these bits from these two registers are logically or?d to produce the address of the word in memory. see figure 21. word and byte main memory access using main memory access instructions, the hs-rtx2010rh can perform either word or single byte main memory accesses, as well as byte swapping within 16-bit words. bit 12 of the memory access opcode (see table 16), is used to determine whether byte or word operations are to be performed (where bit 12 = 0 signi?s a word operation, and bit 12 = 1 signi?s a byte operation). in addition, the determination of whether a byte swap is to occur depends on whether addressing mode 0 or mode 1 is in effect (as determined by bit 2 of the ), and on whether an even or odd address is being accessed (see figures 26 and 27). dpr cpr dpr cpr top ubr upr ubr cr figure 26. memory access (word) figure 27. memory access (byte) 0 11 0 0 1 0 0 1 0 0 1 1 1 0 1 15 8 7 0 15 8 7 0 processor memory 15 87 0 15 8 7 0 processor memory 15 8 7 0 15 87 0 processor memory 15 87 0 15 87 0 processor memory word write word read word write word read 0 0 0 0 ir bit 12 cr bit 2 address even/odd data access (16-bit) byte read processor memory 0 15 8 7 0 15 87 0 byte write processor memory unchanged 15 8 7 0 15 8 7 0 byte write processor memory 15 8 7 0 15 8 7 0 unchanged byte read processor memory 0 15 8 7 0 15 8 7 0 1 1 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 data access (8 -bit) address even/odd bit 2 cr bit 12 ir hs-rtx2010rh
28 whenever a word of data is read by a data memory operation into the processor, it is first placed in the register. by the time the instruction that reads that word of data is completed, however, the data may have been moved, optionally inverted, or operated on by the alu, and placed in the register. whenever a data memory operation writes to memory, the data comes from the register. the byte order bit is bit 2 of the con?uration register, (see figure 11 in the ?tx internal registers section). this bit is used to determine whether the default (mode 0) or byte swap (mode 1) method will be used in the data memory accesses. word access is designated when the bit 12 = 0 in the memory access opcode, and can take one of two forms, depending upon the status of , bit 2. when bit 2 = 0, the mode 0 method of word access is designated. word access to an even address (a0 = 0) results in an unaltered transfer of data, as shown in figure 26. word access to/from an odd address (a0 = 1) while in this mode will effectively cause the byte order bit to be complemented and will result in the bytes being swapped. when the bit 2 = 1, the mode 1 method of word access is designated. access to an even address (a0 = 0) results in a data transfer in which the bytes are swapped. word access to an odd address (a0 = 1) while in this mode will effectively cause the byte order bit to be complemented with the net result that no byte swap takes place when the data word is transferred. see figure 26. byte access is designated when the bit 12 = 1 in the memory access opcode, and can also take one of two forms, depending on the value of bit 2. when the bit 2 = 0, a byte read from an even address in mode 0 causes the upper byte (md15-md08) of memory data to be read into the lower byte position (md07-md00) of , while the upper byte (md15-md08) is set to 0. a byte write operation accessing an even address will cause the byte to be written from the lower byte position (md07-md00) of into the upper byte position (md15-md08) of memory. the data in the lower byte position (md07-md00) in memory will be left unaltered. accessing an odd address for either of these operations will cause the byte order bit to be complemented, with the net result that no swap will occur. see figure 27. when bit 2 = 1, the mode 1 method of memory access is used. accessing an even address in this mode means that a byte read operation will cause the lower byte of data to be transferred without a swap operation. a byte write in this mode will also result in an unaltered byte transfer. conversely, accessing an odd address for a byte operation while in mode 1 will cause the byte order bit to be complemented. in a byte read operation, this will result in the upper byte (md15-md08) of data being swapped into the lower byte position (md07-md00), while the upper byte is set to 0 (md15-md08 set to 0). see figure 27. a byte write operation accessing an odd address will cause the byte to be swapped from the lower byte position (md07-md00) of the processor register into the upper byte position (md15-md08) of the memory location. the data in the lower byte position (md07-md00) in that memory location will be left unaffected. note: these features are for main memory data access only, and have no effect on instruction fetches, long literals, or user data memory. subroutine calls and returns the rtx can perform both ?hort?subroutine calls and ?ong?subroutine calls. a short subroutine call is one for which the subroutine code is located within the same code page as the call instruction, and no processor cycle time is expended in reloading the . performing a long subroutine call involves transferring execution to a different code page. this requires that the be loaded with the new code page as described in the memory access section, followed immediately by the subroutine call instruction. this adds two additional cycles to the execution time for the subroutine call. for all instructions except subroutine calls or branch instructions, bit 5 of the instruction code represents the subroutine return bit. if this bit is set to 1, a return is performed whereby the return address is popped from the return stack, as indicated in figure 19. the page for the return address comes from the . the contents of the register are written to the , and the contents of the are written to the so that execution resumes at the point following the subroutine call. the return stack is also popped at this time. hs-rtx2010rh software the hs-rtx2010rh is designed around the same architecture as the rtx 2000, and is a hardware implementation of the virtual forth engine. as such, it does not require the additional assembly or machine language software development typical of most real-time microcontrollers. the instruction set for the hs-rtx2010rh tforth compiler combines multiple high level instructions into single machine instructions without having to rely on either pipelines or caches. this optimization yields an effective throughput which is faster than the processors clock speed, while avoiding the unpredictable execution behavior exhibited by most risc processors caused by pipeline ?shes and cache misses. 2010 compilers intersil offers a complete ansi c cross development environment for the hs-rtx2010rh. the environment provides a powerful, user-friendly set of software tools next top next cr ir cr cr cr ir cr cr next next cr cpr cpr ipr i pc ipr cpr hs-rtx2010rh
29 designed to help the developers of embedded real-time control systems get their designs to market quickly. the environment includes the optimized ansi c language compiler, symbolic menu driven c language debugger, rtx assembler, linker, pro?er, and prom programmer interface. the hs-rtx2010rh tforth compiler from intersil translates forth-83 source code to hs-rtx2010rh machine instructions. this compiler also provides support for all of the hs-rtx2010rh instructions speci? to the processors registers, peripherals, and asic bus. see the tables in the following sections for instruction set information. table 6. instruction set summary notations definition m-read read data (byte or word) from memory location addressed by contents of register into register. m-write write contents (byte or word) of register into memory location addressed by contents of register. g-read read data from the asic address (address field ggggg of instruction) into register. a read of one of the on- chip peripheral registers can be done with a g-read command. g-write write contents of register to asic address (address field ggggg of instruction). a write to one of the on-chip peripheral registers can be done with a g-write command. u-read read contents (word only) of user space location (address field uuuuu of instruction) into register. u-write write contents (word only) of register into user space location (address field uuuuu of instruction). swap exchange contents of and registers. dup copy contents of register to register, pushing previous contents of onto stack memory. over copy contents of register to register, pushing original contents of to register and original contents of register to stack memory. drop pop parameter stack, discarding original contents of register, leaving the original contents of in and the original contents of the top stack memory location in . inv perform 1? complement on contents of register, if i bit in instruction is 1. alu-op perform appropriate cccc or aaa alu operation from table 20 on contents of and registers. shift perform appropriate shift operation (ssss field of instruction) from table 21 on contents of and/or registers. d push short literal d from ddddd field of instruction onto parameter stack (where ddddd contains the actual value of the short literal). the original contents of are pushed into , and the original contents of. are pushed onto stack memory. d push long literal d from next sequential location in program memory onto parameter stack. the original contents of are pushed into , and the original contents of are pushed onto stack memory. r perform a return from subroutine if bit = 1. note: all unused opcodes are reserved for future architectural enhancements. top top next top top top top top top next top next next next top top next next top next top next top top next top next top next next top next next table 7. instruction register bit fields (by function) function code definition ggggg address field for asic bus locations uuuuu address field for user space memyyory locations cccc aaa alu functions (see table 20) ddddd short literals (containing a value from 0 to 31) ssss shift functions (see table 21) hs-rtx2010rh
30 table 8. hs-rtx2010rh and access operations (note) operation (g-read, g-write) return bit value asic address ggggg register function read mode 0 00000 pushes the contents of into (with no pop of the return stack) read mode 1 00000 pushes the contents of into , then performs a subroutine return write mode 0 00000 pops the contents of into (with no push of the return stack) write mode 1 00000 performs a subroutine return, then pushes the contents of into read mode 0 00001 pushes the contents of into , popping the return stack read mode 1 00001 pushes the contents of into without popping the return stack, then executes the subroutine return write mode 0 00001 pushes the contents of into popping the parameter stack write mode 1 00001 performs a subroutine return, then pushes the contents of into read mode 0 00010 pushes the contents of shifted left by one bit, into (the return stack is not popped) read mode 1 00010 pushes the contents of shifted left by one bit, into (the return stack is not popped), then performs a subroutine return write mode 0 00010 pushes the contents of into as a ?tream count, indicating that the next instruction is to be performed a specified number of times; the parameter stack is popped write mode 1 00010 performs a subroutine return, then pushes the stream count into read mode 0 00111 pushes the contents of into read mode 1 00111 pushes the contents of into , then performs a subroutine return write mode 0 00111 performs a subroutine call to the address contained in , popping the parameter stack write mode 1 00111 pushes the contents of onto the return stack before executing the subroutine return note: see the rtx programmers reference manual for a complete listing of typical software functions. i pc i i top i i top i top i i top i i i top i i top i top i i top i i i top i i top i top i i i pc pc top pc pc top pc top pc top table 9. hs-rtx2010rh reserved i/o opcodes instruction code operation 15 14 13 12 111098 7654 3210 1 0 1 1 0000 10r0 1101 select 1 0 1 1 0000 00r0 1101 select 1 0 1 1 0000 10r1 0000 set softint 1 0 1 1 0000 00r1 0000 clear softint dpr cpr table 10. subroutine call instructions instruction code operation 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 a a a a a a a a a a a a a a a call word address aaaa aaaa aaaa aaa0, in the page indicated by . this address is produced when the processor performs a left shift on the address in the instruction code. subroutine call bit (bit 15 = 0: call, bit 15 = 1: no call) cpr hs-rtx2010rh
31 table 11. subroutine return instruction code operation 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - r - - - - - return from subroutine subroutine return bit (note) (bit 5, r = 0: no return r = 1: return) note: does not apply to subroutine call or branch instructions. a subroutine return can be combined with any other instruction (as implied here by hyphens). table 12. branch instructions instruction code operation 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 0 b b a a a a a a a a a drop and branch if = 0 1 0 0 0 1 b b a a a a a a a a a branch if = 0 1 0 0 1 0 b b a a a a a a a a a unconditional branch 1 0 0 1 1 b b a a a a a a a a a branch and decrement if 0; pop if = 0 branch address (note) note: see the programmers reference manual for further information regarding the branch address ?ld. top top i i i i table 13. register and i/o access instructions instruction code operation 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 0 0 0 i 0 0 r g g g g g g-read drop inv 1 0 1 1 1 1 1 i 0 0 r g g g g g g-read inv 1 0 1 1 c c c c 0 0 r g g g g g g-read over alu-op 1 0 1 1 0 0 0 i 1 0 r g g g g g dup g-write inv 1 0 1 1 1 1 1 i 1 0 r g g g g g g-write inv 1 0 1 1 c c c c 1 0 r g g g g g g-read swap alu-op table 14. short literal instructions instruction code operation 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 0 0 0 i 0 1 r d d d d d d drop inv 1 0 1 1 1 1 1 i 0 1 r d d d d d d inv 1 0 1 1 c c c c 0 1 r d d d d d d over alu-op 1 0 1 1 1 1 1 i 1 1 r d d d d d d swap drop inv 1 0 1 1 c c c c 1 1 r d d d d d d swap alu-op hs-rtx2010rh
32 table 15. long literal instructions instruction code operation (1st cycle) (2nd cycle) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 1 0 0 0 i 0 0 r 0 0 0 0 0 d swap inv 1 1 0 1 1 1 1 i 0 0 r 0 0 0 0 0 d swap swap inv 1 1 0 1 cccc 0 0 r 0 0 0 0 0 d swap swap over alu-op 1 1 0 1 1 1 1 i 1 0 r 0 0 0 0 0 d swap drop inv 1 1 0 1 cccc 1 0 r 0 0 0 0 0 d swap alu-op table 16. memory access instructions instruction code operation (1st cycle) (2nd cycle) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 s 0 0 0 i 0 0 r 0 0 0 0 0 m-read swap inv 1 1 1 s 1 1 1 i 0 0 r 0 0 0 0 0 m-read swap swap inv 1 1 1 s cccc 0 0r 0 0 0 0 0 m-read swap swap over alu-op 1 1 1 s 000p 0 1r 0 0 0 0 0 (swap drop) dup m-read swap nop 1 1 1 s 111p 0 1r d d d d d (swap drop) m-read d nop 1 1 1 s aaap 0 1r d d d d d (swap drop) dup m-read swap d swap alu-op nop 1 1 1 s 0 0 0 i 1 0 r 0 0 0 0 0 over swap m-write inv 1 1 1 s 1 1 1 i 1 0 r 0 0 0 0 0 over swap m-write drop inv 1 1 1 s cccc 1 0r 0 0 0 0 0 m-read swap alu-op 1 1 1 s 000p 1 1r 0 0 0 0 0 (over swap) swap over m-write nop 1 1 1 s 111p 1 1r d d d d d (over swap) m-write d nop 1 1 1 s aaap 1 1r d d d d d (over swap) swap over m-write d swap alu-op nop if (p = 0), perform either (swap drop) or (over swap) if s = 0, memory is accessed by word if s = 1, memory is accessed by byte note: swap d swap d rot hs-rtx2010rh
33 table 17. user space instructions instruction code operation 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (1st cycle) (2nd cycle) 1 1 0 0 0 0 0 i 0 0 r u u u u u u-read swap inv 1 1 0 0 1 1 1 i 0 0 r u u u u u u-read swap swap inv 1 1 0 0 cccc 0 0 r u u u u u u-read swap swap over alu-op 1 1 0 0 0 0 0 i 1 0 r u u u u u dup u-write inv 1 1 0 0 1 1 1 i 1 0 r u u u u u dup u-write drop inv 1 1 0 0 cccc 1 0 r u u u u u u-read swap alu-op table 18. alu function instructions instruction code operation 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 0 0 0 0 i 0 0 r 0 s s s s inv shift 1 0 1 0 1 1 1 i 0 0 r 0 s s s s drop dup inv shift 1 0 1 0 cccc 0 0 r 0 s s s s over swap alu-op shift 1 0 1 0 0 0 0 i 0 1 r 0 s s s s swap drop inv shift 1 0 1 0 1 1 1 i 0 1 r 0 s s s s drop inv shift 1 0 1 0 cccc 0 1 r 0 s s s s alu-op shift 1 0 1 0 0 0 0 i 1 0 r 0 s s s s swap drop dup inv shift 1 0 1 0 1 1 1 i 1 0 r 0 s s s s swap inv shift 1 0 1 0 cccc 1 0 r 0 s s s s swap over alu-op shift 1 0 1 0 0 0 0 i 1 1 r 0 s s s s dup inv shift 1 0 1 0 1 1 1 i 1 1 r 0 s s s s over inv shift 1 0 1 0 cccc 1 1 r 0 s s s s over over alu-op shift table 19. step math functions (note 25) instruction code operation 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 0 - - - - - - - 1 - - - - (see the programmer? reference manual) note: 25. these instructions perform multi-step math functions such as multiplication, division and square root functions. use of either the streamed instruction mode or masking of interrupts is recommended to avoid erroneous results when performing step math operations. unsigned division: load dividend into and load divisor into execute single step form of d2 (note 25) instruction 1 time execute opcode a41a 1 time execute opcode a45a 14 times execute opcode a458 1 time the quotient is in , the remainder in square root operations: load value into and load 8000h into load 0 into execute single step form of d2 (note 25) instruction 1 time execute opcode a51a 1 time execute opcode a55a 14 times execute opcode a558 1 time the root is in , the remainder in top next md next top top next sr md next top hs-rtx2010rh
34 table 20. alu logic functions/opcodes cccc aaa function 0010 001 and 0011 nor 0100 010 swap- 0101 swap-c with borrow 0110 011 or 0111 nand 1000 100 + 1001 +c with carry 1010 101 xor 1011 xnor 1100 110 - 1101 -c with borrow table 21. shift functions shift ssss name function status of c register register t15 tn t0 n15 nn n0 0000 no shift cy z15 zn z0 tn15 tnn tn0 0001 0< sign extend cy z15 z15 z15 tn15 tnn tn0 0010 2* arithmetic left shift z15 z14 zn-1 0 tn15 tnn tn0 0011 2*c rotate left z15 z14 zn-1 cy tn15 tnn tn0 0100 cu2/ right shift out of carry 0 cy zn+1 z1 tn15 tnn tn0 0101 c2/ rotate right through carry z0 cy zn+1 z1 tn15 tnn tn0 0110 u2/ logical right shift 0 0 zn+1 z1 tn15 tnn tn0 0111 2/ arithmetic right shift z15 z15 zn+1 z1 tn15 tnn tn0 1000 n2* left shift of cy z15 zn z0 tn14 tnn-1 0 1001 n2*c rotate left cy z15 zn z0 tn14 tnn-1 cy 1010 d2* 32-bit left shift z15 z14 zn-1 tn15 tn14 tnn-1 0 1011 d2*c 32-bit rotate left z15 z14 zn-1 tn15 tn14 tnn-1 cy 1100 cud2/ 32-bit right shift out of carry 0 cy zn+1 z1 z0 tnn+1 tn1 1101 (note) cd2/ 32-bit rotate right through carry tn0 cy zn+1 z1 z0 tnn+1 tn1 1110 ud2/ 32-bit logical right shift 0 0 zn+1 z1 z0 tnn+1 tn1 1111 d2/ 32-bit right shift z15 z15 zn+1 z1 z0 tnn+1 tn1 note: see the programmers reference manual. where: t15-most significant bit of tn-typical bit of t0-least significant bit of n15-most significant bit of nn-typical bit of n0-least significant bit of c-carry bit cy-carry bit before operation zn-alu output z15-most significant bit 15 of alu output tnn-original value of typical bit of top next next next top top top next next next next hs-rtx2010rh
35 table 22. mac/barrel shifter/lzd instructions instruction code operation 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 0 0 0 0 0 0 r 0 1 0 0 0 forth 0 = 1 0 1 1 0 0 0 0 0 0 r 0 1 0 0 1 double shift right arithmetic 1 0 1 1 0 0 0 0 0 0 r 0 1 0 1 0 double shift right logical 1 0 1 1 0 0 0 0 0 0 r 0 1 1 0 0 clear mac accumulator 1 0 1 1 0 0 0 0 0 0 r 0 1 1 1 0 double shift left logical 1 0 1 1 0 0 0 0 0 0 r 0 1 1 1 1 floating point normalize 1 0 1 1 0 0 0 0 0 0 r 1 0 0 0 1 shift mac output regs right 1 0 1 1 0 0 0 0 0 0 r 1 0 0 1 0 streamed mac between stack and memory 1 0 1 1 0 0 0 0 1 0 r 1 0 0 1 0 streamed mac between asic bus and memory 1 0 1 1 0 0 0 0 0 0 r 1 0 0 1 1 mixed mode multiply 1 0 1 1 0 0 0 0 1 0 r 1 0 1 1 0 unsigned multiply 1 0 1 1 0 0 0 0 1 0 r 1 0 1 1 1 signed multiply 1 0 1 1 0 0 0 0 0 0 r 1 0 1 0 0 signed multiply and subtract from accumulator 1 0 1 1 0 0 0 0 0 0 r 1 0 1 0 1 mixed mode multiply accumulate 1 0 1 1 0 0 0 0 0 0 r 1 0 1 1 0 unsigned multiply accumulate 1 0 1 1 0 0 0 0 0 0 r 1 0 1 1 1 signed multiply accumulate 1 0 1 1 1 1 1 0 0 0 r 1 0 0 1 0 load mxr register 1 0 1 1 1 1 1 0 0 0 r 1 0 1 1 0 load mlr register 1 0 1 1 1 1 1 0 0 0 r 1 0 1 1 1 load mhr register 1 0 1 1 1 1 1 0 1 0 r 1 0 0 1 0 store mxr register 1 0 1 1 1 1 1 0 1 0 r 1 0 1 1 0 store mlr register 1 0 1 1 1 1 1 0 1 0 r 1 0 1 1 1 store mhr register hs-rtx2010rh
36 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site www.intersil.com die characteristics die dimensions: 364 mils x 371 mils x 21 mils 1mil interface materials: glassivation: type: sio 2 thickness: 8k ? 1k ? top metallization: type: al/si/cu thickness: 7.5k ? 2k ? substrate: tsos5 cmos, silicon on sapphire backside finish: silicon assembly related information: substrate potential: unbiased (sos) additional information: worst case current density: 1.0 x 10 5 a/cm 2 metallization mask layout hs-rtx2010rh ma16 (53) ma15 (52) ma14 (51) vcc (50) ma13 (49) ma12 (48) ma11 (47) ma10 (46) ma09 (45) gnd (44) ma08 (43) ma07 (42) ma06 (41) ma05 (40) ma04 (39) ma03 (38) ma02 (37) ma01 (36) gd00 (35) gd01 (34) gd02 (33) gnd (32) gd03 (31) gd04 (30) gd05 (29) gd06 (28) vcc (27) gd07 (26) gd08 (25) gd09 (24) gd10 (23) gd11 (22) gd12 (21) gnd (20) gd13 (19) gd14 (18) gd15 (17) gio (16) gr/ w (15) iclk (14) wait (13) reset (12) (11) ei5 (10) ei4 (9) ei3 (8) ei2 (7) ei1 (6) vcc (5) intsup (4) nmi (3) inta (2) tclk (cqfp pin 1) ga02 (84) ga01 (83) ga00 (82) md15 (81) gnd (80) md14 (79) md13 (78) md12 (77) md11 (76) md10 (75) md09 (74) md08 (73) vcc (72) md07 (71) md06 (70) md05 (69) gnd (68) md04 (67) md03 (66) md02 (65) md01 (64) md00 (63) mr/ w (62) pclk (61) boot (60) new (59) uds (58) lds (57) gnd (56) ma19 (55) ma18 (54) ma17 hs-rtx2010rh

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